IBM PPC440X5 Manual do Utilizador descarregar pdf (Página 297)

100

101

dcbi

Data Cache Block Invalidate

Preliminary PPC440x5 CPU Core User’s Manual

instrset.fm.

September 12, 2002 Page 297 of 589

dcbi

Data Cache Block Invalidate

EA ← (RA|0) + (RB)

DCBI(EA)

An effective address (EA) is formed by adding an index to a base address. The index is the contents of

If the data block at the EA is in the data cache, the data block is marked invalid, regardless of whether or not

the memory page referenced by the EA is marked as cacheable. If modified data existed in the data block

prior to the operation of this instruction, that data is lost.

If the data block at the EA is not in the data cache, no operation is performed.

If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.

Registers Altered

• None

Invalid Instruction Forms

• Reserved ﬁelds

Programming Notes

Execution of this instruction is privileged.

Exceptions

This instruction is considered a “store” with respect to Data Storage exceptions. See Data Storage Interrupt

on page 181 for more information.

This instruction is considered a “store” with respect to data address compare (DAC) Debug exceptions. See

Debug Interrupt on page 195 for more information.

dcbi RA, RB

31 RA RB 470

0 6 11 16 21 31

1 2 ... 292 293 294 295 296 297 298 299 300 301 302 ... 589 590

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IBM PPC440X5 Manual do Utilizador Página 297

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