IBM PPC440X5 Manual do Utilizador descarregar pdf (Página 298)

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101

dcbst

Data Cache Block Store

PPC440x5 CPU Core User’s Manual Preliminary

Page 298 of 589

instrset.fm.

September 12, 2002

dcbst

Data Cache Block Store

EA ← (RA|0) + (RB)

DCBST(EA)

An effective address (EA) is formed by adding an index to a base address. The index is the contents of

If the data block at the EA is in the data cache and marked as modified, the data block is copied back to main

storage and marked as unmodified in the data cache.

If the data block at the EA is in the data cache, and is not marked as modified, or if the data block at the EA is

not in the data cache, no operation is performed.

The operation specified by this instruction is performed whether or not the memory page referenced by the

EA is marked as cacheable.

If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.

Registers Altered

• None

Invalid Instruction Forms

• Reserved ﬁelds

Exceptions

This instruction is considered a “load” with respect to Data Storage exceptions. See Data Storage Interrupt on

page 181 for more information.

This instruction is considered a “store” with respect to data address compare (DAC) Debug exceptions. See

Debug Interrupt on page 195 for more information.

dcbst RA, RB

31 RA RB 54

0 6 11 16 21 31

1 2 ... 293 294 295 296 297 298 299 300 301 302 303 ... 589 590

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IBM PPC440X5 Manual do Utilizador Página 298

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